1. Technical Field
Apparatuses and methods consistent with exemplary embodiments relate to interface technologies, and more particularly, to an interface circuit configured to transmit and receive data according to a communication protocol.
2. Description of the Related Art
An interface circuit or device is used to transmit and receive data between electronic devices. Recently, as performance of an electronic device continuously improves, an interface circuit or device having wide bandwidth is needed. In particular, an interface technology based on a related art peripheral component interconnect express (hereinafter it is referred to as PCIe) protocol is widely used as a high speed serial interface technology.
An 8b/10b encoding is used in the related art first generation PCIe protocol and the related art second generation PCIe protocol. According to the 8b/10b encoding, data having a length of ten bits is generated by adding a bit string of two bits to data of eight bits. The generated data is serially transmitted according to the PCIe protocol. In this case, the bit string of two bits is added to cause the number of logic values of ‘0’ and logic values of ‘1’, which are included in data being serially transmitted, to be equal. However, the added bit string of two bits occupies 20 percent of the length (i.e., ten bits) of data being serially transmitted. Thus, when the 8b/10b encoding is used, bandwidth efficiency is degraded.
A 128b/130b encoding is used in the related art third generation PCIe protocol. According to the 128b/130b encoding, information data has a length of 128 bits. Additionally, sync header data of two bits, indicating whether the information data of 128 bits is general data or control data, is added to the information data of 128 bits. According to the 128b/130b encoding, the length (i.e., 128 bits) of the information data is much greater than the length (i.e., two bits) of the sync header data. Thus, when the 128b/130b encoding is used, bandwidth efficiency is improved.
According to the PCIe protocol, a clock and data recovery (hereinafter referred to as CDR) circuit is included in a data receiving unit. The CDR circuit extracts clock information of a data transmission unit from data being input. Then, the CDR circuit recovers original data by sampling data input, based on the extracted clock information. According to the 8b/10b encoding, a data string of data input to the CDR circuit includes the same number of logic values of ‘0’ and logic values of ‘1’. Thus, according to the 8b/10b encoding, the logic values of the data string of the data input to the CDR circuit transits enough to extract the clock information.
However, according to the 128b/130b encoding, the logic values of the data string of the data input to the CDR circuit may not sufficiently transit. According to the 128b/130b encoding, in the worst case, the data string of the data input to the CDR circuit may include 129 successive logic values of ‘0’ or logic values of ‘1’. In this case, the CDR circuit cannot extract the clock information of the data transmission unit and, as a result, original data cannot be recovered.